The World Leader in High Performance Signal Processing SolutionsPC Board Layout Techniques for FAEsHigh Speed, Mixed-Signal & Low Level Applications
The Art of PCB DesignGood PCB design is a discipline that takes years to master.Reliable High-speed, mixed-signal designs require a great deal of theoretical knowledge and practical understanding to be done properly.We’ll cover many important concepts at a high level Confidential2
AgendaPCBs 101Good High-Speed PCB Design PracticeszThe Power of Power and Ground planeszProper use of decoupling capacitorszThe True Nature of Resistors and Capacitors in High-speed DesignszHigh-speed Signal Propagation -Wires or Transmission Lines?zImpedance Mismatches, Series and Parallel TerminationzManaging EMIMixed Signal PCB LayoutzGrounding Mixed Signal Data Acquisition SystemzGround Plane in Mixed Signal DesignszPower Filtering & decouplingzParasitic ConsiderationzControl Differential line impedanceSmall Signal LayoutzConsider Track Resistor LosszProper grounding shielding cablezMinimize PCB Leakage by Guard RingzPrevent PCB Heating Temperature SensorsADI Confidential3
PCB BasicsPCB Units of MeasurementPCB methodologies originated in the United States Units of measurement are therefore typically in Imperial units, not SI/metric dimensions are commonly measured in thickness & conductor length and width typically measured in inches and “mils”.1 mil = inches1 mil = .0254 mmzConductor thickness measured in ounces (oz).The weigh of conductor metal in a square foot of material.Typical = µ = µ = µ = µmADI Confidential4
Copper FoilPCB BasicsPrepregPCB Stack-upCorePrepregCoreCross Section of a typical 8-layer stack-up PrepregCorePrepregA PCB consists of alternating layers of prepregand core materialsMaterials:zCore: A thin piece of cureddielectric (usually FR4 : fiberglass & epoxy) zPrepreg: Short for preimpregnated. A thin piece of uncured dielectric (usually “FR4”: fiberglass-epoxy). Prepreg melts into an epoxy glue when heated and pressed, and then hardens / cures with the same dielectric constant as the core material. zCopper Foil : Thin piece of copper that is bonded / laminated toboth sides of the core using epoxy resin.The number of layers of copper foil corresponds to the “layers of the PCB”zAn 8-layer PCB has 8 layers of copper foil.Stack-up is symmetrical about the center of the board in the vertical axis to avoid mechanical stress in the board under thermal Confidential5
PCB (Printed Circuit Board) AnatomyPCB Conductors : Tracesρ⋅Lρ⋅LLR===RsAh⋅WWCu resistivity: ρ=-8ΩmSource: (Cu) is the most commonly used conductor in and/or connectors may be plated in nickel followed by gold to provide a corrosion-resistant electrically conductive.Trace Width (W) and Length (L) –controlled by PCB layout engineerzWidth and spacing between traces typically ≥5 mil in common fabrication processesTrace Thickness (h) –variable of fabrication processzTypically –3oz zTrend towards Signal Integrity Tip:All of the above affect the resistance, capacitance and impedance of the trace and must be well understood for high-speed Confidential6
PCB BasicsPCB Conductors : Power PlanesCopper FoilSignal tracePrepregPower planeCorePrepregCorePrepregCorePrepregPower PlaneszA solid layer of copper used to provide power or use thicker copper layer than signal layers to reduce resistance.Why are they needed?zProvide a stable, low-impedance path for power and ground signals to all devices on the PCBzShield signals between layers to minimize cross-talkSignal Integrity Tip: By placing power and ground on opposite sides of thin core material, we can maximize the “intra-plane capacitance”. Also, this minimizes PCB Confidential7
PCB BasicsPCB Insulators / DielectricsCommon Dielectric MaterialszFR-4 (Woven fiberglass and epoxy)Most commonly used, widely available, relatively low-costDielectric constant (permittivity) : Max, @ 500 MHz, @ 1 GHzzAcceptable for signals up to about 2 GHz (loss and cross-talk will increase beyond this)Fairly rigid (17 GPausing Young’s modulus)zFR-2 (Phenoliccotton paper)Very low-cost, used in cheap consumer devices.Susceptible to crackingDielectric constant (permittivity) : @ 1 GHzzCEM-3 (Woven glass and epoxy)Very similar to FR4, widely used in JapanzPolyimideGood performance at high frequencieszFR & CEMFR : Flame RetardantCEM : Composite Epoxy MaterialSignal Integrity Tip: Most PCB insulator materials support a relatively controlled dielectric -this is important for maintaining a constant impedance for transmission lines! zMore on this soonADI Confidential8
PCB BasicsViasViaBlind ViaBuried ViaVias (plated holes)zUsed to connect layerszFormed by drilling or punching hole through PCB layers and plating the insidezTypically much larger than signal tracesBuried and Blind ViaszProvide increased wiring densityzAdded cost to PCB fabrication –typically used only in high-volumezBuried vias are difficult to debugSignal Integrity Tip: vias introduce capacitance and change the characteristic impedance of a Confidential9
PCB FabricationPCB BasicsTypical PCB Design ProcessFabrication Tolerance(. min trace width, min hole size, etc.)SchematicDRC ReportPCBSchematic DRC ReportCapturePCB NetlistGerber FilesLayoutSchematic Drill FileLibraryFootprint LibraryPCB ParametersLibrarian and/or (. core material, device providercopper weight, etc)DRC = Design Rule CheckADI Confidential10
PCB BasicsTypical PCB Fabrication Gerber files, Drill files and other PCB attributes from the PCB substrate and laminate (core) film is attached to the substrate material (. FR4). layer image -resist chemical is masked and cured (hardened) over copper film where copper is to remain (. traces and vias).-cured chemical is washed to copper film (typically FeClor Ammonia). Unmasked copper is dissolved. applied to remove the cured washed to remove all , cleaning & plating vias is how connections are made between drilled through layer stack where vias are immersed in plating solution where a thin layer of copper forms within -plating then used to deposit around 1mil of layer image (text and graphics)ADI Confidential11
Good High-Speed PCB Design Practices OverviewSome customers still design PCBs by “feel”and not using proper methodologies and/or discipline. For modern high-speed analog and digital design, it is almost impossible to produce a reliable design based on “feel”.Result may bezImproper or unexpected system behaviorzUnacceptable levels of noise in analog pathszSystem stability/reliability that varies across temperature and/or board build bit-errors between connected devices on same PCBzLarge amounts of power supply and ground noisezOver-shoot, under-shoot and glitching on Confidential12
Good High-Speed PCB Design Practices Using the Right EquipmentA good oscilloscope with ample bandwidth is an essential tool in high-speed PCB to consider the bandwidth and sampling frequency of the device.What will a 133MHz SDRAM signal look like on a low-cost scope with 200MHz bandwidth and 2GSPS sampling rate?zImportant events like glitching, overshoot and undershoot, and power supply noise may not be properly How are these related?represented on a low-cost scope. Remember! High-speed digital signals are square waves!zSquare waves are rich in high-energy, odd harmonics 11x(t)=sin(t)+sin(3t)+sin(5t)...35zAs process geometry decreases (130nm->90nm->65nm), rise and fall times decrease = more harmonics! ADI Confidential13
Good High-Speed PCB Design PracticesPower and Ground PlanesPower and ground planes should always be used when possible. Why?zProvides a low-impedance path between the power supply and the devices in the shieldingzProvide heat dissipationPulse response with and without zReduces stray inductancea ground planeA solid, unbroken plane is best. (source Analog Dialogue: Volume 39, September 2005)zBreaks in the ground plane can introduce parasitic inductance in traces above or below the plane.Remember!zAt low frequency, current will follow the path of least resistance. zAt high frequency, current will follow the path of least Confidential14
Generally Good PCB Design PracticesDecoupling Capacitors (or “bypass”caps)VDDintWhen gates within a device switch, there is an instantaneous change in impedance within the is an instantaneous change in Decoupling capacitors provide GATEa low-impedance current source for these instantaneous voltage fluctuation on VDDthe ground and power ensure power and voltage GNDHigh to lowsignals are within the operating Low to high transitionVDDspecification of the Confidential15
Good High-Speed PCB Design PracticesDecoupling CapacitorsFive broad frequency bands need to be “bypassed”with high-speed devicesSUPPLY, VzDC to 10kHzTaken care of by the +(+5%)regulator+(+%)+ to 100kHz+(%)+(-5%)Taken care of by electrolytic bypass capacitors+(+5%)z100kHz to 10MHz+(+%)+Taken care of by multiple +(%)100nF ()+(-5%)z10MHz to 100MHzNOTE SUPPLY VOLTAGE DROPS BELOW 5% LIMIT DURING SWITCHING TRANSIENTS AND DURING HEAVY CURRENT Taken care of by multiple DEMAND CAUSED BY INCREASED PROGRAM ACTIVITY10nF ()z100MHz and aboveThis device is operating out of Taken care of by multiple specification! Ample oscilloscope bandwidth is essential for detecting 1nF & PCB Power & these events. Ground PlanesADI Confidential16VVVVDDDDIINNTTDDDDEEXXTT
Good High-Speed PCB Design PracticesDecoupling CapacitorsHow many decoupling capacitors are required?zSystem dependent! Need to consider frequency of operation, number of I/O pins switching, Capacitive load on each pin, trace impedance, junction temperature, internal chip operation, etc. For processors, consider the variety of internal operations likecache, internal memory accesses, DMA, etc. etc. rule of thumb: At all frequencies from DC, to well above thehighest clock frequencies, the supply pins should have less than ±5% of VDD total tolerance of the maximum DC supply voltage drift PLUS the peak noise amplitude must be less than 5% of the nominal supply voltage.An oscilloscope with ample bandwidth is required.Various methods exist for estimating the total required capacitance and how to distribute the capacitance across a number of smallervalue capacitors This is a complex problem, particularly when dealing with the complexities of modern processors which contain millions of gates.Numerous application notes on semiconductor ADI Confidential17
Good High-Speed PCB Design PracticesDecoupling CapacitorsFor best performance, minimize the inductance ABSOLUTELY NOT!BETTERand resistance between the device supply pins and the decoupling capacitors.PCB traces and vias EVEN BETTEREVEN BETTER STILLintroduce impedance!THE BEST!SOLID VIA WITHIN PADADI Confidential18
Good High-Speed PCB Design PracticesDecoupling CapacitorsWhen ground/power plane pairs are used, capacitors can be just as effective on the top side of the SMD CAPACITOR1mm BALL PITCH(63×31 mils)L = 10mmMini-BGA (17x17mm)h= 12-mil‘A’AGNDs = -4h= 46-mil‘X’(62-mil)B‘B’VIAS DIAM, d = (12-mil)NOTE: DRAWING IS NOT TO SCALEADI Confidential19
Good High-Speed PCB Design PracticesDecoupling CapacitorsEffective bypassing at frequencies over 100MHz…zAs clock frequencies and edge rates increase it becomes more difficult to effectively bypass the power supply pins of high-frequency devices.Capacitor ESL (Effective Series Inductance) results in increasing reactance with frequencyCapacitor ESR (Effective Series Resistance) increases, reducing the effectiveness of capacitorsCapacitor parasitic mounting (pads, vias) reactance increases with frequency100nF capacitors are useless above 100MHzADI Confidential20
Good High-Speed PCB Design PracticesUnderstanding Capacitors -ESLESL (Effective Series Inductance) is caused by the inductance of the electrodes and leads of the capacitor.The ESL of a capacitor sets the limiting factor of how well (or fast) a capacitor can de-couple noise off a power buss.Capacitors are essentially an L-C circuit thus they have a resonant point. The ESL and the capacitance thus both affect the resonate-point of a capacitor.Capacitors with a high resonant frequency will perform ADI Confidential21
Good High-Speed PCB Design PracticesUnderstanding Capacitors -ESLSource: ADI Confidential22
Good PCB Design PracticesUnderstanding CapacitorsDifferent types of capacitors…zTBAADI Confidential23
High Speed PCB Design and Layout Understanding ResistorsJames Bryant’s paperzTBAADI Confidential24
High Speed PCB Design and LayoutWire or Transmission Line?Wire or Transmission Line?zWire –we consider every point of a wire to be at the same potential at any given point in timezTransmission Line –we consider the effects of signal propagation and assume that points along the transmission line will be at different voltage potentials as signals traverse.When to treat a signal path as a transmission line?zIf the length is greater than 1/100 of the the receiving device is edge the system is not tolerant of excessive overshoot and always! Source: Johnson & Graham, High-Speed Digital Design (AHandbook of Black Magic) ADI Confidential25
High Speed PCB Design and LayoutPropagation : Time and DistancePropagation Delay : the rate at which an electrical signal travels through a medium. zTypically measured in picoseconds/inch.Electrical signals propagate at a speed dependent on the surrounding delay increases proportionally to the square root ofthe dielectric constantMediumDelay (ps/in)Dielectric ConstantVacuumSpeed of light : (radio waves)85~ Cable (75% velocity) Cable (66% velocity) PCB (outer trace) PCB (inner trace) PCB (inner trace)240-2708-10ADI Confidential26
High Speed PCB Design and LayoutTransmission Lines and Impedance MismatchERABWhen the impedance of a conductor changes a portion of the signal energy is reflected.The amount of energy reflected is proportional to the difference in impedance between the two −ZBAE∝RZ+ZBAADI Confidential27
High Speed PCB Design and LayoutUnderstanding Trace ImpedanceThe physical characteristics of the PCB trace will have a large effect on the materialzWidth of tracezTrace thicknesszProximity to other traces and planeszDielectric constants of surrounding materials (. air, FR4, etc).Many free tools available to help estimate the impedance of a :// Confidential28
High Speed PCB Design and LayoutChanges in Impedance Across Signal PathtracetracetracecabletraceDevice ADevice BviaviaconnectorconnectorLoadOutput DriverTransmission LineZ≈1MΩZ≈25ΩtypicaltypicalZ≈50ΩtypicalDevice A to Device B, a propagating signal will likely traverse multiple impedance changes.The largest mismatches will almost always occur at the source and loadzWill generate large reflections!zHow can we deal with this?Let’s look at a story…ADI Confidential29
The Story of EDGAR the Energy PacketCourtesy of Bob KilgoreEdgar is a joggerHe travels at a rate of 6 inches / nanosecond on a Printed Circuit BoardHe changes the voltage of conductors that he touchesADI Confidential30
Edgar Meets The “Unterminated”Transmission lineAttributes:zPoint to point connectionz25 Ohm impedance Output Driverz50 ohm impedance Transmission Line (Z)0z1 Meg Ohm impedance receiverDriverReceiverTransmission LineADI Confidential31
At The StartThe Driver lowers the voltage by from VDD to Confidential32
Edgar Starts for the ReceiverEdgar travels at 6 inches per nanosecondDriverReceiverTransmission LineADI Confidential33
Edgar Is REFLECTED!Edgar is moving from a 50Ωtransmission line to 1MΩreceiver!ZL−Z01000000−50=≈1ZL+Z01000000+50Almost 100% of Edgar is reflected back towards the source!ADI Confidential34
Edgar Returns to the DriverEdgar travels at 6 inches per nanosecond with most of his original energy!DriverReceiverTransmission LineADI Confidential35
Edgar Finds the Next ObstacleEdgar meets the 25Ωsource driver after his return journey on the 50 ohm transmission line.The Reflected Energy is:ZL−Z025−501==−ZL+Z025+503ADI Confidential36
Edgar Is Sent to the Receiver AgainEdgar travels at 6 inches per nanosecondDriverReceiverTransmission LineADI Confidential37
Edgar Is Sent to the Driver AgainEdgar travels at 6 inches per nanosecondDriverReceiverTransmission LineADI Confidential38
Edgar Is Sent to the Receiver a Third TimeEdgar travels at 6 inches per nanosecondDriverReceiverTransmission LineADI Confidential39
What would we see on the scope?Measured at the DriverMeasured at the ReceiverVDDGNDAnd what effect might this have on an edge-sensitive input?Always measure at the Receiver not the Driver!ADI Confidential40
High Speed PCB Design and LayoutTransmission Line TerminationLeverage Ohms’law to minimize the impedance mismatch at the source side and load of the transmission line.Managing the Source : zSource impedance is typically less than 50ΩzWe can add a series resistor to the source to increase its impedance to match the transmission technique is called “serial termination”Managing the Load :zLoad impedance is typically much greater than 50ΩzWe can add a parallel resistor to the load to decrease its impedance to match the transmission technique is called “parallel termination”Each method has its pros and cons. A combination of both is often most Confidential41
High Speed PCB Design and LayoutParallel TerminationParallel resistor at the receiver can work well but has: zIncreases drive current and thus increases power Crosstalk, Increased ground bounce or supply noise (depending on if the parallel resistor is pulled high or low).Drive current DriverReceiverabout 50 mATransmission LineADI Confidential42
High Speed PCB Design and LayoutSeries TerminationSeries resistor at the driver is less disruptive:z…but the driver impedance is nonlinear and you lose some energy getting into the transmission lineDriverReceiverTransmission LineADI Confidential43
DDR SDRAM TerminationDDR uses Dual termination.At VCC/2 = , Io of the driver is about 14mADriverReceiverVCC/2Transmission LineADI Confidential44
Edgar Meets DDR in the Real WorldThe Series Resistor Plus the Drive impedance is 50 OhmsThe Parallel Resistor is 50 OhmsThe Transmission Line Impedance is 60 Ohms (Bad PCB)DriverReceiverVCC/25025Transmission LineADI Confidential45
Edgar Finds the First ObstacleThe Receiver is a 50 Ohm Load But the Transmission Line was 60 Ohms Due To FR4 Construction and Fabrication ErrorsThe Reflected Energy is:ZL−Z050−60−1==ZL+Z050+6011ADI Confidential46
Edgar is ReflectedEdgar travels at 6 inches per nanosecondDriverReceiverVCC/2Transmission LineADI Confidential47
Edgar Finds the Next ObstacleThe Driver is a 50 Ohm Load But the Transmission Line was 60 Ohms Due To FR4 Construction and Fabrication ErrorsThe Reflected Energy is:ZL−Z050−60−1==ZL+Z050+6011ADI Confidential48
Edgar is ReflectedEdgar Travels at 6 inches per nanosecondEdgar is now about 1/100 of its original EnergyTherefore Edgar changes the voltage by 1/10 or about voltsDriverReceiverVCC/2Transmission LineADI Confidential49
Good PCB Design PracticesElectro-Magnetic EmissionsTwo primary tenants of electro-magnetism zCurrent passing through a conductor generates a magnetic a conductor in a magnetic field will induce currentThe shape an intensity of a magnetic field generated by passing current through a conductor is affected by the shape of the conductor and visa Confidential50
Good PCB Design PracticesEMI : Electro-Magnetic Interference EMI typically refers to an undesirable amount of electromagnetic emission from a design.EMI from one device on a PCB may affect the performance of another circuits are more likely to be the source of disruptive emissions due to the handling of periodic waveforms and the fast clock/switching rates. zAnalog circuits are more likely to be the susceptible victims due to higher gain functions.EMI from the entire system may affect the performance of other near-by Confidential51
Good PCB Design PracticesReducing EMI in PCBs There are many widely used techniques for minimizing the EMI of a PCB design.Fundamentals:zPower and ground planes providing shieldingTop and bottom ground planes can help reduce radiation from multi-layer boards by at least 10 placement of devices on the PCB –keep analog and digital systems as far apart as possible on the PCBzProper use of decoupling caps reduces power/ground noise and thus EMI from these signal traces away from the edge of the PCBzAvoid right angles in PCB traceszBe cognizant of PCB trace resonance at fundamental frequency or harmonics due to to come… Confidential52
Getting the best performance on our PCBsAs amplifiers and converters’performance improved, achieve their performance on your PCB will be challenging. Layout guide & design notes training before PCB layout will save much time in debugging.Moving on today’s trainingzMixed Signal PCB Layout TechniqueszSmall Signal PCB Layout TechniquesADI Confidential53
The World Leader in High Performance Signal Processing SolutionsMixed Signal PCB LayoutGrounding Data Acquisition SystemADI
Digital Currents Flowing in AnalogReturn Path Create Error VoltagesAnalogCircuitryClockAnalogDigitalCircuitryCircuitryCircuitryDigitalCircuitryClockSensitive Analog Sensitive Analog CircuitryCircuitry Disrupted by Circuitry safe from Digital Supply NoiseDigital Supply NoiseIIDDIIAA++++ANALOGDIGITALANALOGDIGITALVVVVDADACIRCUITSCIRCUITSCIRCUITSCIRCUITSVVININGNDIGNDAREFI+ IIADDREFIDIncorrectCorrectADI Confidential55ResistorResistor
Grounding Mixed Signal ICs with LowInternal Digital Currents: Multiple PC BoardsV= NOISE BETWEEN NVNGROUND PLANESVVDAFILTERVVADBUSRMIXEDANALOGBUFFERDIGITALSIGNALCIRCUITSLATCHCIRCUITSDEVICEAGNDDGNDAAADDANALOGDIGITALGROUND PLANEGROUND PLANEAADDTO SYSTEM TO SYSTEM ANALOG SUPPLYDIGITAL SUPPLYATDOI CSoYnfSidTeEntMial STAR GROUND56
Star Ground System which has Separated Analog and Digital Ground PlanesVVNNVVVVAADDPCBPCBANALOGDIGITALANALOGDIGITALGROUNDGROUNDGROUNDGROUNDPLANEPLANEPLANEPLANEXXXXADADNo No DIGITAL GROUND PLANEconnectionconnectionXBACKXNot Over LayPLANE}XXANALOG GROUND PLANEVAPOWERVHigh Voltage Capacitor may need DSYSTEMhere to provide high frequency SUPPLIESSTARinterference shot cut path (for GROUNDEMC/EMI purpose)XADI Confidential57
The World Leader in High Performance Signal Processing SolutionsMixed Signal PCB LayoutUsing Ground PlaneADI
Characteristics of Ground PlanesDigital Radios frequently have high speed digital logic on the same board as high gain RF electronics. Shielding and Grounding are significant aspects of the receiver should be shielded at the sourcezGround currents should be returned to their sourcezSupply currents should take the path of least resistance & inductance back to the sourceMinimum 1 whole ground layerzOne entire PCB side (or layer) is a continuous ground conductorGives minimum ground resistance and inductance, but itn’talways sufficient to solve all ground problems.Breaks in ground planes can improve or degrade circuit performance –there is no general rulszEliminate the possibility ground loopszCareful attention should be paid to layout to ensure that digital return currents do not flow through analog section of the plane acts as a shieldUsing Mulit-layer (>=4) with ground and voltage plane ADI Confidential59
How to make full use of your Ground Plane?Provide as much ground plane as possiblezEspecially under traces that operate at high frequencyUse thickest metal as feasiblezReduces resistance and provides improved thermal pathzHelps reduce resistive losses due to skin effectMount components that conduct fast rise times or high frequencies as close to the board as possiblezMinimize use of leaded componentsTry to single-point the critical components into the ground plane to avoid voltage drops.Provide as much ground plane as possiblezEspecially under traces that operate at high frequencyUse thickest metal as feasiblezReduces resistance and provides improved thermal path)zHelps reduce resistive losses due to skin effectMount components that conduct fast rise times or high frequencies as close to the board as possiblezMinimize use of leaded componentsTry to single-point the critical components into the ground plane to avoid voltage Analog circuitry to one section and digital circuitry running digital and analogtracks close to each other, this will help avoid coupling digital noise into Confidential60
Grounding example of solid ground planeIecarT Single GND Layer for High Speed pociTrtceleiConverters PCB dnuzCover empty space of TOP / Bottom orGlayer with GND, but no small Iunconnected to connect 2 or more GND layer, as many as possible but do not cut some plane to pieces. ExampleTop SidezThe top layer is solid ground. zThe Bottom has a trace connecting the RF connector to the load. zReturn current flows from the load back to the RF connector, directly above the trace on the opposite sideADI Confidential61Resistor
Grounding Example of split ground planePotential coupling to input Ground LooptransformerADCGround loops are introduced by splitting the two grounds. For example, a digital line that switches at 1 V/nSinto a 10 pFload will generate a 10 mAtransient. zIf 16 lines move at the same time, this is 160 mAof switching current in the loop!ADI Confidential62ResistorDigital
Grounding –DC current vs. AC currentAC current Single GND or Split GND planefollows the zTo be simple, usingsignal GND layer for High path of least Speed Converts layout (>10MHz), no AGND impedanceand DGND layer difference. zSeparated AGND and DGND and connect with signal point only applies in low speed design (less than 1MHz).zSome cut lines allowed to separate difference area, but connection must be bigger than Component (>10mm width). And no signal DC current trace cross cut lines. follows the zIf all frequency range are consider (IE, path of least sampling signal from DC to 50MHz), then resistanceground layer is difficult, need case by case Top Sidestudy.ExamplezIn a broken ground or split ground, the return currents follow the path of least impedance. zAt DC, the current follows the path of least resistance. As the frequency increases, the current follows the path of least there is now a ‘loop’the inductance Bottom sidecan be quite high and an EMI/RFI problem can Confidential63Resistor
Cut lines with goodComponent placement Vin1Vout1AmpADCDACAmpSDRAMGND GND DGND AreaCut Cut LineLineDACAmpADCDSPAmpVout2Vin2LDOLDOClockClockLDOLDOFPGABig Big CapacitorsCapacitorsConnector 1Connector 2Separate Analog area, mixer signal area and pure digital area.No cross over of input and out put.Clock area is an independent area.Power supply is an independent area, especially DC-DC -DC must be a corner, better in an other PCB lines must be used for Capacitors must be in a corner or near PCB boundary. ADI Confidential64
The World Leader in High Performance Signal Processing SolutionsMixed Signal PCB LayoutPower Filter&Decoupling Capacitor consideration
Regulation priorities for power supply systemsCARDCONNECTORTO#1INDIVIDUAL+VRAIL#2S STAGE +VSINPUT#3L1 *++RAILC1μ100F/100μHMULTIPLE25V3-5V NOISY 3-5V CLEAN PINCONTACTSGROUND PLANEINPUT FROM OUTPUT TO C1C2+SWITCHING 300mA LOAD 100μF/20V1μFSUPPLY OR ANALOG COMMONTANTALUMCERAMIC(GND)DC-DC STAGEINPUTCONVERTER* Fastron MESC C2series or μ100F/equivalentR125V1ΩTO-VRAIL#1S INDIVIDUALINPUT#2STAGE -VS#3RAIL--A Card-entry Filter is useful for low medium frequency power line noise filtering in analog systemC (100µF)ESL REGION(20nH)Dual-Supply low frequency rail bypass / distribution filter REGIONfor Power High performance analog power systems use linear |Z|ESR (Ω)regulators,with primary power derived from:REGIONzAC line powerzBattery power systemszDC-DC power conversion systemsESR = ΩRemember Electrolytic Capacitor Impedance vary with 10kHz1MHzFrequencyLOG FREQUENCYADI Confidential66
DC-DC power filterAdded the C-L-C filter to remove to switching noise generated from components have to enclose the DC-DC Vin pin as , C2 need consider switch frequency (50k, 100k, )Via from ++12VPower Switching regulators should be avoided if at all possible, but if not…zApply noise control techniqueszUse quality layout and groundingzBe aware of EMI zADI do not suggest DC-DC power supply as analog power supply, at least add LDODC-DC power supply can be used as digital power supply of ADC or MCV (ADuC702x)Let the DC-DC far away from ADC (or ADuC702x)The C-L-C filter near DC-DC. Still need on each power pin. Big plane in Power layer helps a lot. ADI Confidential67
Grounding and Decoupling PointsFERRITEVVAAVBEADDSEE TEXTAAVVDADRBUFFERADCAMPGATEORORDACTO OTHERRREGISTERDIGITALCIRCUITSAVAAGNDDGNDAAADVOSAMPLINGLTAGEANALOGREFERENCECLOCKVAGROUND PLANEAGENERATORDIGITALGROUND PLANEAADADI Confidential68
Decoupling on SOIC partsCORRECTINCORRECTOPTIONALFERRITE BEADSDECOUPLINGPOWERPOWERDECOUPLINGCAPACITORSUPPLYSUPPLYCAPACITORTRACETRACEV+V+PCBICICTRACEGNDGNDVIAS TOGROUNDVIA TOPLANEGROUNDPLANERULE OF THUMB: VIA RESISTANCE ≈1mΩ, VIA INDUCTANCE ≈1nHLocalized high frequency supply filters provide optimum filtering and decoupling via short low inductance path (ground plane)Rule of Thumb: zVia resistance ≈1mΩ,Via inductance ≈1nHADI Confidential69
GNDNDGGNDDGNGNDDecoupling on LQFP/LFCSP partsVCCCCorrectGNDVCCLQFPViaVCCLFCSPCWrongGNDVCCCWrongGNDCorrectNo long trace under ICzShort trace then to bottom by viaWrongShort trace to GND or Power under your AD9779 Layout like this!Short trace to decouple CapacitorsADI Confidential
Different Capacitors’Impedance vs. FrequencyMuRata 0805 GMR216 Paralleling caps reduces impedance over a wider frequency range.Put the smaller decoupling capcitoras near as possible to power pin. ADI Confidential71
Why every power pin need decoupling Caps?VVADFERRITE BEADADVVDALLPPCSTRAYRRPPDATARBUSBUFFERANALOGDIGITALGATE ORAIN/CIRCUITSCIRCUITSDATAREGISTEROUTAB≈C10pFINCSTRAYRRPPIIADLLPPAGNDDGNDSHORTCONNECTIONSVDNOISEAADI Confidential72A = ANALOG GROUND PLANED = DIGITAL GROUND PLANE
Low Speed High Resolution ADC layout Skills ExampleAD7656 possible issue in Grounding and DecouplingAD7656 Missing code (No VVADcodes between 0 ~ -32)zPoor Grounding and poor power VVsupplyADANALOGDIGITAL+5V AVCC must be very stableCIRCUITSAD7656CIRCUITSHalf AVCC power plan, half DVCC AGNDDGNDSYSTEMpower plan. Use wide trace (>1mm) STARGROUNDfor +/-12V power supply on bottom layer, aviod+/-12V cut AVCC power AADDlayer to piecesANALOGDIGITALSingle point connect AGND and GROUND PLANEGROUND PLANEDGNDzInsufficient decoupleAD220uF Decoupling Cap for each AD7656ANALOGDIGITAL10uF + for each AVCC pin SUPPLYSUPPLY(8pins total)Short but wide trace from Via to AVCC pinLeadless capacitor layoutADI Confidential73
Summary of Power Supply Bypassing & decouplingPlace bypass caps as close to the power supply pins as possibleSMT ferrite beads are very effective in reducing ripple contentHigh Frequency requires ground planezMinimize parasiticsUse stable, well behaved componentszLow drift and low ESRCompletely Analytical Approaches can be difficultzPrototyping is required for optimal resultsUse a combination of paralleled capacitors to achieve frequency rejection of unwanted noise across a wide bandwidthADI Confidential74
The World Leader in High Performance Signal Processing SolutionsMixed Signal PCB LayoutParasiticConsiderationADI
Approximate Trace InductanceLWHAll dimensions are in mm2LW+HμHSTRIP INDUCTANCE = ln + + )()(W+HL1cm of mm PC track has an inductance of nH(H = , W = , L = 1cm)Minimize Inductance Example1) Use Ground plane L= =, W = ) Keep length short: Halving the H = .035mm (1oz copper)length reduces inductance by 44%Strip Inductance = 3) Doubling width only reduces At 10MHz Z= Ωa % error in a 50ΩLinductance by 11% systemADI Confidential76
Trace/Pad E ArC=C = = plate area in mmd = plate separation in mmE = dielectric constant relative to airrK = relative dielectric constantMost common PCB type uses Example: Pad of SOIC glass-fiber epoxy material with E = Capacity of PC track over ground plane L = W = roughly Capacitance2 A = ) Increase board thickness d = ) Reduce trace/pad area 3) Remove ground plane C = Confidential77
BASIC PRINCIPLES OF COUPLING INTERFERENCE CIRCUITSIGNAL CIRCUITCAPACITIVE COUPLING EQUIVALENT CIRCUIT MODELCM = MUTUAL INDUCTANCEB = MAGNETIC FLUX DENSITYINA = AREA OF SIGNAL LOOPVZωV= 2πf= FREQUENCY OF NOISE SOURCECOUPLED1NNNV = INDUCED VOLTAGE = ωMI= ωABNNZ= CIRCUIT IMPEDANCE1 BASIC PRINCIPLES OF INDUCTIVE COUPLINGZ2 = 1/jωCZ1⎛⎜V= V)COUPLEDNZZ⎝1 + 2ADI Confidential78
CAPACITOR EQUIVALENT CIRCUIT AND RESPONSE TO INPUT CURRENT PULSEI= 1APEAK iINPUTdi1AvCURRENT=dt100nsESR = ΩEquivalent f = = 20nHdiV=ESL•PEAKdt+ESR•I=400mVPEAKC = 100µFOUTPUTVOLTAGEX= Ω CESR •I= 200mVPEAK@ Confidential79
Via ParasiticsVia CapacitanceVia εTDr1⎡4h⎤⎛⎞C=L=2hln+1⎜⎟nHD−D⎢⎥21d⎝⎠⎣⎦D= diameter of clearance hole in the 2ground plane, cmL = inductance of the via, nHD= diameter of pad surrounding via, cm1 H = length of via, cmT = thickness of printed circuit board, cmεD = diameter of via, cmr= relative electric permeability of circuit board materialConsider a power supply pin of an op C = parasitic via capacitance, pFamp that goes through a via to the power plane of an cm thick board, the Consider a signal coming from the diameter of the via is cm back of the board to the top of the board through a via. Board thickness = , ⎡4()⎤⎛⎞L=2()ln+1⎜⎟⎢⎥D= D= ⎝⎠⎣⎦L = = Confidential80
rParasitic ModelResistor Parasitic ModelCapacitor Parasitic ModelLRRPSLCPCRCDADAC = CapacitorR= insulation resistance PR= equivalent series resistance (ESR)SRL = series inductance of the leads and plates R = ResistorR= dielectric absorptionC= Parallel capacitanceDAPC= dielectric absorptionDAL= equivalent series inductance (ESL)ADI Confidential81
Stray Capacitance & Stray Inductance at inverting inputRFPADPAD+VPADStray CapacitanceTRACEVIARGPADPADRFTRACEVO+VPADPADPADTRACEVRIGPADPADVIAPADRLVStray InductanceiPADRL-V-VLow Frequency Op Amp SchematicHigh Frequency Op Amp ModelADI Confidential82
Stray Capacitance SimulationV113U11+56OUT2-0AD8055an/% overshoot R31R21V21-5V1k1k00C8V341V1pfR11Pulse Response with 1pF Stray Capacitance1500001pF stray capacitance Reduce peaking1) Increase board thickness 2) Reduce trace/pad area 3) Remove ground plane 4) Lower Resistance Frequency Response with 1pF Stray CapacitanceADI Confidential8347V-V+
Stray Inductance Simulation Schematic1””=29nHV11L73U11+56OUT29nH2-0AD8055an/ADR31R21V21-51k1k0V31AD8055Pulse Response With and Without Ground PlaneR11150Approximately over Confidential8447V-V+
RFRLRLLayouts –What to do and not do!Remove ground plane Vias and long return distance under Negative input to Even a few pF on summing adds several nHreduce input capacitancejunction can destabilize op ampRFXDisableNCInput GroundsDisableNC+V-InRsCIR+V-InCsIV+INoutV+INoutNCC-VsNC-VsCBad PCB layoutGood PCB layoutReduce return path length to reduce InductanceADI Confidential85
Electrolytic BypassCeramicPower Supply BypassingElectrolytic CeramicBypassADXXXXADXXXXIncorrectCorrect ADI Confidential86Electrolytic BypassCeramicElectrolytic BypassamicCer
SOIC Layout ExampleRFDisableRGVoutVINCR1CCeramicElectrolyticBypassBypassCompCap-VSADI Confidential87ElectrolyticBypass
AD8099 Layout Example+VSElectrolyticCeramic BypassVOBypass0402DisablecomponentsRLRRGFCR1CVINCeramic CCBypassElectrolyticBypass-VSADI Confidential88
The World Leader in High Performance Signal Processing SolutionsMixed Signal PCB LayoutControl Differential Line ImpedanceADI
Typical LVDS Driver in CMOSV+V–OUTPUT DRIVER+)()V–V++ΩΩA standard LVDS driver in nominal current is , and the common-mode voltage is .The swing on each input at the receiver is ()therefore 350mV p-pwhen driving a 100Ωdifferential termination resistor. zThis corresponds to a differential swing of 700mV Confidential90
Differential Line impedanceswwtεr= ~ @εr604hZodiff(Ω)=[*ln[]*(+d)εr+ Confidential91
Control Differential Line Impendence8mil8mil1/2ozTop LayerRX0+RX0-RX1+RX1-6milDielectric LayerControl differential line impendencezTrace characteristic impedance will be around 54 Ohm single / 102 Ohm differential on ½OZ copper () with dielectric of . After coating, it will change about 5-12 Ohm. zDistance between Differential line pair should be greater than 30mil to avoid interference of adjacent pairs.Lower down the length of differential lineszIt’s better to control >100MHz clock or RF signal trace length lessthan 2 inch. Routing differential signal pair together and minimize the totalnumbers of via on each trace as few as possible.Recommend softwarezPolar Si6000ADI Confidential92
Measuring the TMDS pair impedanceTDR (Time Domain Reflector) OhmReflectionsTDRStepGeneratorWaveformDigitizerHigh SpeedS/HADI Confidential93
The Visual lumped interconnect analysis using TDRADI Confidential94
Summary Mixed Signal Layout TechniquesUse ground planezHigh speed applications require low impedance returnszHelps minimize parasitics ParasiticszParasitic capacitance, inductance and resistance can ruin the best designed circuitzLayout is critical!Shielding Long WireControl Differential Line ImpendenceADI Confidential95
The World Leader in High Performance Signal Processing SolutionsSmall Signal PCB Layout Consider loss on Track Resistor
Calculation of Sheet resistance (For Standard Copper PCB) ρZR =XYρ = RESISTIVITYRZYXSHEET RESISTANCE CALCULATION FOR1 OZ. COPPER CONDUCTOR:–6ρ Ω= X 10cm, Y = = mΩXZ= NUMBER OF SQUARESXR = SHEET RESISTANCE OF 1 SQUARE (Z=X)Ω= Confidential97
Long Track Resistance Impact on ADC5cmSIGNAL16-BIT ADC,SOURCER = 5kΩ (10 mils) wide,1 oz. copper PCB traceAssume ground pathresistance negligibleOHM’sLaw predicts >1 LSB of error due to drop in PCB a 16-bit ADC with a 5kΩinput resistance, zPCB track is 5cm of wide 1 oz. zThe track resistance of nearly Ω.zThe resulting voltage drop is a gain error of (~%), zOver 1LSB (% for 16 bits). ADI Confidential98
Small Common Ground Currents can degrade Precision Amplifier Accuracy+5VU1AD8551R1V99kΩIN5mV FSVOUTIR2SUPPLY700μA1kΩΩG1G2ΔV ≅ 7μVA low-level signal Vof 5mV FS, Design required to precisely gain of an AD8551 chopper-stabilized amplifier for best dc AD8551 Spec: Low offset voltage: 1 μV, offset drift: μV/°CAt the load end, the signal Vis measured with respect to G2, the local ground. OUTzBecause of the small 700μA Iof the AD8551 flowing between G1 and G2, there is a SUPPLY7μV ground error on Ground 7 times the typical input offset expected from the op amp!ADI Confidential99
A More Realistic Model of a Ground System+VsSIGNALHIGH SIGNAL ADCCURRENT SOURCECIRCUITZiG1IG2ΔVWith changes,this becomes "star" groundAny current flow through a common ground impedance can cause errorsΔV = (I + i) * Z zZ: The impedance between G1 and G2 zI: Signal related : The effect of any non-signal related Confidential100
The World Leader in High Performance Signal Processing SolutionsSmall Signal PCB Layout Proper Grounding Shielding Cable
Ground loops in shield twisted pair cableBRIDGEANDA1A2RTDCONDITIONINGINCIRCUITSNCVNGND 1GND 2BRIDGEANDRTDCONDITIONINGCIRCUITS“HYBRID”Ground loops in shield twisted pair GROUNDCcable can cause errorsVCauses Current in Shield (Usually N50/60Hz)Differential Error Voltage is Produced at Input of A2 Unless:Hybrid grounding of shielded zA1 Output is Perfectly Balanced andcable with passive sensorzA2 Input is Perfectly Balanced andzCable is Perfectly BalancedADI Confidential102
Impedance-balanced Driver of Balanced Drive of Balanced Shielded Cable & Coaxial CablesCOAX CABLER/2SA1A2A1A2R/2SDIFFAMPCShield Carries Signal Return CurrentR/2SA1A2A1A2R/2SSINGLE-ENDEDAMPCImpedance-balanced driver of Coaxial cables can use either balanced drive of balanced shielded balanced or single-ender receiverscableaids noise-immunity with either balanced or single end source signalsADI Confidential103
Transmitter low level IF/RF signal with Micro-Strip lineDIELECTRICHTRACEWWGROUND, TPOWERTBPLANESHDIELECTRICHEMBEDDEDTRACEGROUND PLANEA micro-strip transmission line with defined impedance is formed by a PCB trace of appropriated geometry, spaced from a ground plane.A Symmetric strip line transmission line with defined impedance is formed by a PCB trace of appropriate geometry embedded between equally spaced ground and/or power planes.ADI Confidential104
The pros and cons of not embedded vsthe embedded signal trace in multi-layer PCB designNOT EMBEDDEDEMBEDDEDRoutePowerPowerRouteGroundRouteRouteGroundFast switching signals (clocks etc) should be shieldedzUsing digital ground to avoid radiating noisezClock signals should never be run near analoginputs of the deviceszAvoid cross over of digital and analogsignals.Advantages of embedded traceszSignal traces shielded and protectedzLower impedance, thus lower emissions and crosstalk zSignificant improvement > 50MHzDisadvantages of embedded traceszDifficult prototyping and troubleshootingzDecoupling may be more difficultzImpedance may be too low for easy matchingADI Confidential105
The World Leader in High Performance Signal Processing SolutionsSmall Signal PCB Layout Minimize PCB Leakage by Guard Ring
Using Guard-Rings Minimizes PCB Leakage PathsBoard leakage is an error111x10100kin the output+5vI-50pAvoltage at lowD+5v50pAlevel -5vVoutLeakage current from + to -Vthrough FR4in SOT23-5 package is 50XInput bias current-5vVout+VAD8067-V+IN-INInvertingGuard-Ring Layout for SOT-23Guard-Ring Layout for SOIC / MSOPADI Confidential107
NON-INVERTING MODE GUARD:Guard PatternsYRING SURROUNDS ALL "HOT NODE"LEAD ENDS - INCLUDING INPUTTERMINAL ON THE PCBINVERTING MODE GUARD:XYRRING SURROUNDS ALL LEADLYENDS AT THE "HOT NODE"AND NOTHING ELSELOW VALUE GAINExample application:YRESISTORSPhotodiode PreampsUSE SHIELDING (Y) ORUNITY-GAIN BUFFER (X) IF GUARD HAS LONGLEADINVERTING MODE GUARD ENCLOSES ALL OP NON-INVERTING MODE GUARD ENCLOSES ALL OP AMP AMP INVERTING INPUT CONNECTIONS WITHIN NON-INVERTING INPUT CONNECTIONS WITHIN A LOW A GROUNDED GUARD RINGIMPEDANCE, DRIVEN GUARD RINGNOTE: PINS 1, 5, & 8 ARE OPEN ON MANY “R”PACKAGED DEVICES18GUARD1827GUARD2INPUT7INPUT3636GUARD455GUARD4–VS–VSINVERTING MODENON-INVERTING MODEGUARD PATTERNGUARD PATTERNPCB GUARD PATTERNS FOR INVERTING AND NON-INVERTING MODE OP AMPS USING 8 PIN SOIC (R) PACKAGEADI Confidential108
Summary of PCB Layout Skills For Low PCB Leakage ApplicationsIncluding photodiodes, pressure sensors, and other high source impedance inputs#1) Use a CMOS or JFET input amplifier#2) Minimize the PC-board leakage currentzKeep trace lengths as short as possiblezUse guard rings around the input pins#3) Keep the board CLEAN!!zDirt and oil are a major cause of PC-board leakage currentADI Confidential109
The World Leader in High Performance Signal Processing SolutionsSmall Signal PCB Layout Minimize PCB Heating Temperature Sensors
Minimize PCB Heating Temperature SensorsBasicsHeat Transfer•The transfer of heat is normally from a high temperature object to a lower temperature object.•Heat transfer from a cold region to a hot region can be done by forcing the system . refrigerators, to perform the energy transfer.•Heat transfer is accomplished by three basic methods –•Conduction•Convection•RadiationConductionConvectionRadiationADI Confidential111
Minimize PCB Heating Temperature SensorsBasics Heat Transfer Theory -ConductionExcellent Temperature Conductive MaterialThermal conductivityMaterial•Conduction is the most prevalent heat W/m·Ktransfer method in pcbsDiamond1000-2600Silver406•If one end of a PCB is at a higher temperature, Copper385then energy will be transferred down the PCB Gold320towards the colder end. The higher speed Aluminium205Brass109particles will collide with the slower ones with a Platinum70net transfer of energy to the slower ones. The of conduction heat transfer is: = (K x A (T–T) / = Energy conducted in time (joules/second) = Thermal conductivity of the copper (385 W/(m·K) @ room temp)Expanded polystyrene ("beadboard") = Area of copper on pcbAir (300 K, 100 kPa) = TemperatureSilica = Distance between hot and cold Confidential112
Minimize PCB Heating Temperature SensorsCorrect PCB layout for measuring ambient temperature•Many designers don’t want to measure the Main Heat SourceTempPCB temperature(uController)Sensor•Just want to measure the ambient air temperature•Problem is, how do you prevent the heat from the PCB heat sources affecting the ambient temperature measurement of the temp sensorTips for ambient temperature measurement•Use a hatched GND plane. Reduce GND plane area therefore increasing thermal resistance.•Keep the temp sensor as far away from heat sources as possible.•Use a separate GND plane for the temp sensor and keep connections to main GND plane as low as possible.•Use narrow GND connections as this will increase thermal resistance.•Use solid GND plane under main heat source and expose green solder mask. This will give the min thermal resistance for the MHS to dissipate Confidential113
Minimize PCB Heating Temperature SensorsSummary...•Most customers will want to use IC Temp Sensors to measure the temperature of the PCB or a component.•Therefore it is better to use this pcb layout technique. H = (K x A (T–T) / LHOTCOLDH = Energy conducted in time (joules/second)K = Thermal conductivity of the copper (385 W/(m·K) @ room temp)A = Area of GND planeT = TemperatureL = Distance between hot and cold bodies•There will be some customers that want to monitor air temperature and also use the accuracy, linearity, speedy response and convenience of an IC temp sensor.•Therefore they should use this pcb layout Confidential114
BackupADI Confidential115
Further References1.“High-Speed Digital Design -A Handbook of Black Magic”, Howard W. Johnson, Martin Graham, Prentice-Hall, 1993, ISBN 0-13-395724-12.“Tolerance Calculations in Power Distribution Networks”, IstvanNovak, Sun Microsystems, Note published in XcellJournal, Summer 2004. Available at .“Power Distribution System (PDS) Design; Using Bypass/Decoupling Capacitors”, Mark Alexander, Xilinx Application Note, XAPP623 () April 20044.“Decoupling Basics”, Arch Martin, AVX Corp Application Note, 5.“The Effects of ESR & ESL in Digital Decoupling Applications”, Jeffrey Cain, ., AVX Corp Application Note6.“High Speed PCB Design & System Design”, Course notes, Instructor Lee Ritchie, UC Berkeley Engineering Extension, May .“Bypass Capacitor Selection for High-Speed Designs”, Micron Technical Note, TN-00-068.“Effective Decoupling Radius of Capacitor”, H. Chen, J. Fang, W. Shi, paper presented at 2001 EPEP .“ESR & Bypass Capacitor Self Resonant Behavior –How to Select Bypass Caps”, Douglas Brooks, UltraCADDesign, Inc., 200010.“Optimum Placement of Decoupling Capacitors on Packages & PrintedCircuit Boards Under the Guidance of Electromagnetic Field Simulation”, Y. Chen, Z. Chen, J. Fang, Conf’Proc’, 46th Electronic Components & Technology Conf, Orlando Fl, .“Low-Impedance Power Delivery Over Broad Frequencies”, J. Fang, J. Zhao, Printed Circuit Design & Manufacture, Sept, .“Right the First Time –A Practical Handbook on High Speed PCB & System Design”, Lee W. Ritchey, Speeding Edge, May 2003, ISBN 0-9741936-0-7ADI Confidential116
PCB BasicsViasVias (plated holes)zUsed to connect layerszFormed by drilling or punching hole through PCB and plating the insidezTypically much larger than signal tracesBlind Signal Integrity Tip: PCBs introduce capacitance and change the characteristic impedance of a Confidential117
PCB BasicsVias TypesVias (plated holes)zUsed to connect layerszTypically much larger than signal tracesADI Confidential118
