Silicon Substrate
P+
~2um
~725um
Silicon Epi Layer
P−
选择衬底
• 晶圆的选择
– 掺杂类型（N或
P）
– 电阻率（掺杂浓
度）
– 晶向
• 高掺杂(P+)的Si晶
圆
• 低掺杂(P−)的Si外
延层
1
Silicon Substrate P+
Silicon Epi Layer P−
Pad Oxide
热氧化• 热氧化
– 形成一个SiO2薄层，厚度约20nm
– 高温，H2O或O2气氛
– 缓解后续步骤形成的Si3N4对Si衬底造成的
应力
2
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Si3N4淀积• Si3N4淀积
– 厚度约250nm
– 化学气相淀积(CVD)
– 作为后续CMP的停止层
3
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Photoresist
光刻胶成形
• 光刻胶成形
– 厚度约~
– 光刻胶涂敷、曝光和显影
– 用于隔离浅槽的定义
4
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Photoresist
Si3N4和SiO2刻蚀
• Si3N4和SiO2刻蚀
– 基于氟的反应离子刻蚀(RIE)
5
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Photoresist
Transistor Active
Areas
Isolation Trenches
隔离浅槽刻蚀
• 隔离浅槽刻蚀
– 基于氟的反应离子刻蚀(RIE)
– 定义晶体管有源区
6
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Transistor Active
Areas
Isolation Trenches
除去光刻胶
• 除去光刻胶
– 氧等离子体去胶，把光刻胶成分氧化为气
体
7
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Future PMOS Transistor
Silicon Dioxide
Future NMOS Transistor
No current can flow
through here!
SiO2淀积
• SiO2淀积
– 用氧化物填充隔离浅槽
– 厚度约为~，和浅槽深度和几何
形状有关
– 化学气相淀积(CVD)
8
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Future PMOS Transistor Future NMOS Transistor
No current can flow
through here!
化学机械抛光
• 化学机械抛光(CMP)
– CMP除去表面的氧化层
– 到Si3N4层为止
9
Silicon Substrate P+
Silicon Epi Layer P-
Future PMOS Transistor Future NMOS Transistor
除去Si3N4
• 除去Si3N4
– 热磷酸(H3PO4)湿法刻蚀，约180℃
10
Trench Oxide
Cross Section
Bare Silicon
平面视图
• 完成浅槽隔离(STI)
11
Silicon Substrate P+
Silicon Epi Layer P-
Future PMOS Transistor Future NMOS Transistor
Photoresist
光刻胶成形
• 光刻胶成形
– 厚度比较厚，用于阻挡离子注入
– 用于N-阱的定义
12
Silicon Substrate P+
Silicon Epi Layer P-
Future NMOS Transistor
Photoresist
N- Well
Phosphorous (-) Ions
磷离子注入
• 磷离子注入
– 高能磷离子注入
– 形成局部N型区域，用于制造PMOS管
13
Silicon Substrate P+
Silicon Epi Layer P-
Future NMOS TransistorN- Well
除去光刻胶
14
Photoresist
Silicon Substrate P+
Silicon Epi Layer P-
Future NMOS TransistorN- Well
光刻胶成形
• 光刻胶成形
– 厚度比较厚，用于阻挡离子注入
– 用于P-阱的定义
15
Silicon Substrate P+
Silicon Epi Layer P-
Photoresist
N- Well
Boron (+) Ions
P- Well
• 硼离子注入
– 高能硼离子注入
– 形成局部P型区域，用于制造NMOS管
硼离子注入
16
Silicon Substrate P+
Silicon Epi Layer P-
N- Well P- Well
除去光刻胶
17
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
退火
• 退火
– 在600~1000℃的H2环境中加热
– 修复离子注入造成的Si表面晶体损伤
– 注入杂质的电激活
– 同时会造成杂质的进一步扩散
– 快速加热工艺(RTP)可以减少杂质的扩散
18
Trench Oxide
N- Well
P- Well
Cross Section
• 完成N-阱和P-阱
平面视图
19
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Sacrificial Oxide
牺牲氧化层生长
• 牺牲氧化层生长
– 厚度约25nm
– 用来捕获Si表面的缺陷
20
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
除去牺牲氧化层
• 除去牺牲氧化层
– HF溶液湿法刻蚀
– 剩下洁净的Si表面
21
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Gate Oxide
栅氧化层生长
• 栅氧化层生长
– 工艺中最关键的一步
– 厚度2~10nm
– 要求非常洁净，厚度精确(±1Å)
– 用作晶体管的栅绝缘层
22
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Polysilicon
多晶硅淀积
• 多晶硅淀积
– 厚度150~300nm
– 化学气相淀积(CVD)
23
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Photoresist
Channel Length
Polysilicon
光刻胶成形
• 光刻胶成形
– 工艺中最关键的图形转移步骤
– 栅长的精确性是晶体管开关速度的首要决
定因素
– 使用最先进的曝光技术——深紫外光
(DUV)
– 光刻胶厚度比其他步骤薄
24
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Photoresist
Channel Length
多晶硅刻蚀
• 多晶硅刻蚀
– 基于氟的反应离子刻蚀(RIE)
– 必须精确的从光刻胶得到多晶硅的形状
25
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Gate Oxide
Poly Gate Electrode
除去光刻胶
26
Trench Oxide
N- Well
P- Well
Cross Section
Polysilicon
平面视图• 完成栅极
27
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Gate Oxide
Poly Gate Electrode
Poly Re-oxidation
多晶硅氧化
• 多晶硅氧化
– 在多晶硅表面生长薄氧化层
– 用于缓冲隔离多晶硅和后续步骤形成的
Si3N4
28
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Photoresist
光刻胶成形
• 光刻胶成形
– 用于控制NMOS管的衔接注入
29
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Photoresist
Arsenic (-) Ions
N Tip
NMOS管衔接注入
• NMOS管衔接注入
– 低能量、浅深度、低掺杂的砷离子注入
– 衔接注入用于削弱栅区的热载流子效应
30
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N Tip
除去光刻胶
31
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Photoresist
N Tip
光刻胶成形
• 光刻胶成形
– 用于控制PMOS管的衔接注入
32
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Photoresist
BF2 (+) Ions
N TipP Tip
• PMOS管衔接注入
– 低能量、浅深度、低掺杂的BF2+离子注入
– 衔接注入用于削弱栅区的热载流子效应
PMOS管衔接注入
33
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N TipP Tip
除去光刻胶
34
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Silicon Nitride
Thinner Here
Thicker Here
N TipP Tip
P Tip
Si3N4淀积• Si3N4淀积
– 厚度120～180nm
– CVD
35
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Spacer Sidewall
N TipP Tip
P Tip
Si3N4刻蚀• Si3N4刻蚀
– 水平表面的薄层Si3N4被刻蚀，留下隔离侧
墙
– 侧墙精确定位晶体管源区和漏区的离子注
入
– RIE
36
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Photoresist
N TipP Tip
光刻胶成形
• 光刻胶成形
– 用于控制NMOS管的源/漏区注入
37
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
Photoresist
Arsenic (-) Ions
N+ Drain N+ Source
P Tip
NMOS管源/漏注入
• NMOS管源/漏注入
– 浅深度、重掺杂的砷离子注入，形成了重
掺杂的源/漏区
– 隔离侧墙阻挡了栅区附近的注入
38
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ Source
P Tip
除去光刻胶
39
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ Source
Photoresist
P Tip
光刻胶成形
• 光刻胶成形
– 用于控制PMOS管的源/漏区注入
40
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
BF2 (+) Ions
Photoresist
N+ Drain N+ SourceP+ SourceP+ Drain
PMOS管源/漏注入
• PMOS管源/漏注入
– 浅深度、重掺杂的BF2+离子注入，形成了重
掺杂的源/漏区
– 隔离侧墙阻挡了栅区附近的注入
41
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ SourceP+ Drain
Lightly Doped “Tips”
除去光刻胶和退火
• 除去光刻胶和退火
– 用RTP工艺，消除杂质在源/漏区的迁移
42
Trench Oxide Polysilicon
Cross Section
N- Well
P- Well
N+ Source/Drain
P+
Source/Drain
Spacer
平面视图
• 完成晶体管源/漏极，电子器件形成
43
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
除去表面氧化物
• 除去表面氧化物
– 在HF溶液中快速浸泡，使栅、源、漏区的
Si暴露出来
44
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
Titanium
Ti淀积• Ti淀积
– 厚度20~40nm
– 溅射工艺
– Ti淀积在整个晶圆表面
45
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
Titanium Silicide
Unreacted Titanium
TiSi2形成
• TiSi2形成
– RTP工艺，N2气氛，800℃
– 在Ti和Si接触的区域，形成TiSi2
– 其他区域的Ti没有变化
– 称为自对准硅化物工艺(Salicide)
46
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
Titanium Silicide
Ti刻蚀
• Ti刻蚀
– NH4OH+H2O2湿法刻蚀
– 未参加反应的Ti被刻蚀
– TiSi2保留下来，形成Si和金属之间的欧姆
接触
47
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
BPSG淀积
• 硼磷硅玻璃(BPSG)淀积
– CVD，厚度约1um
– SiO2并掺杂少量硼和磷
– 改善薄膜的流动性和禁锢污染物的性能
– 这一层绝缘隔离器件和第一层金属
48
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
BPSG抛光
• 硼磷硅玻璃(BPSG)抛光
– CMP
– 在BPSG层上获得一个光滑的表面
49
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Photoresist
光刻胶成形
• 光刻胶成形
– 用于定义接触孔(Contacts)
– 这是一个关键的光刻步骤
50
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Photoresist
接触孔刻蚀
• 接触孔刻蚀
– 基于氟的RIE
– 获得垂直的侧墙
– 提供金属和底层器件的连接
51
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
除去光刻胶
52
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Titanium Nitride
TiN淀积• TiN淀积
– 厚度约20nm
– 溅射工艺
– 有助于后续的钨层附着在氧化层上
53
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Titanium Nitride
Tungsten
钨淀积• 钨淀积
– CVD
– 厚度不少于接触孔直径的一半
– 填充接触孔
54
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
钨抛光• 钨抛光
– CMP
– 除去表面的钨和TiN
– 留下钨塞填充接触孔
55
Trench Oxide Polysilicon
Cross Section
N- Well
P- Well
N+ Source/Drain
P+
Source/Drain
Spacer
Contact
平面视图
• 完成接触孔，多晶硅上的接触孔没有出现
在剖面图上
56
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Ti (200Å) - electromigration shunt
TiN (500Å) - diffusion barrier
Al-Cu (5000Å) - main conductor
TiN (500Å) - antireflective coating
Metal1淀积
• 第一层金属淀积(Metal1)
– 实际上由多个不同的层组成
– 溅射工艺
57
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
光刻胶成形
• 光刻胶成形
– 用于定义Metal1互连
58
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
Metal1刻蚀
• Metal1刻蚀
– 基于氯的RIE
– 由于Metal1由多层金属组成，所以需要多
个刻蚀步骤
59
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
除去光刻胶
60
Trench Oxide Polysilicon
Cross Section
N- Well
P- Well
N+ Source/Drain
P+
Source/Drain
Spacer
Contact
Metal1
平面视图
• 完成第一层互连
61
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1
IMD淀积
• 金属间绝缘体(IMD)淀积
– 未掺杂的SiO2
– 连续的CVD和刻蚀工艺，厚度约1um
– 填充在金属线之间，提供金属层之间的绝
缘隔离
62
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1
IMD抛光
• IMD抛光
– CMP
63
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1
Photoresist
光刻胶成形
• 光刻胶成形
– 用于定义通孔(Vias)
64
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
IMD1
通孔刻蚀
• 通孔刻蚀
– 基于氟的RIE，获得垂直的侧墙
– 提供金属层之间的连接
65
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1
除去光刻胶
66
Tungsten
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
TiN和钨淀积
• TiN和钨淀积
– 同第一层互连
67
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
钨和TiN抛光
• 钨和TiN抛光
– 同第一层互连
68
Trench Oxide Polysilicon
Cross Section
N- Well
P- Well
N+ Source/Drain
P+
Source/Drain
Spacer
Contact
Metal1
Via1
平面视图• 完成通孔
69
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
Metal2
Metal2淀积
• Metal2淀积
– 类似于Metal1
– 厚度和宽度增加，连接更长的距离，承载
更大的电流
70
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
IMD1 W Via Plug
Metal2
光刻胶成形
• 光刻胶成形
– 相邻的金属层连线方向垂直，减小层间的
感应耦合
71
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
IMD1 W Via Plug
Metal2
Metal2刻蚀
• Metal2刻蚀
– 类似于Metal1
72
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
Metal2
除去光刻胶
73
Trench Oxide Polysilicon
Cross Section
N- Well
P- Well
N+ Source/Drain
P+
Source/Drain
Spacer
Contact
Metal1
Via1
Metal2
平面视图
• 完成第二层互连，后面的剖面图将包括
右上角的压焊点
74
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
PassivationMetal2
钝化层淀积
• 钝化层淀积
– 多种可选的钝化层，Si3N4、SiO2和聚酰亚
胺等
– 保护电路免受刮擦、污染和受潮等
75
Silicon Substrate P+
Silicon Epi Layer P-
P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
Passivation
Bond Pad
Poly Gate
Gate Oxide
Silicide Spacer
Metal2
钝化层成形
• 钝化层成形
– 压焊点打开，提供外界对芯片的电接触
76
Cross Section
Trench Oxide
N+ Source/Drain
P+
Source/Drain
Spacer
Contact
Metal1
Polysilicon Via1
+5V
Supply
VOUT
N- Well
P- Well
Metal2
Ground
Bond Pad
VIN
平面视图
• 完成，显示了电气连接和部分压焊点
77
完成
78
